High-speed_transceiver_logic

High-speed transceiver logic

High-speed transceiver logic

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High-speed transceiver logic or HSTL is a technology-independent standard for signaling between integrated circuits.[1] The nominal signaling range is 0 V to 1.5 V, though variations are allowed, and signals may be single-ended or differential. It is designed for operation beyond 180 MHz.

The following classes are defined by standard EIA/JESD8-6 from EIA/JEDEC:

  • Class I (unterminated, or symmetrically parallel terminated)
  • Class II (series terminated)
  • Class III (asymmetrically parallel terminated)
  • Class IV (asymmetrically double parallel terminated)

Note that Symmetric parallel termination means that the termination resistor at the load is connected to half the output buffer's supply voltage. Double parallel termination means that parallel termination resistors are fitted at both ends of the transmission line.

See also

References

  1. [1]
    "High Speed Transceiver Logic (HSTL). A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits, JESD8-6" (PDF). 1995-08-01.


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